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# rt nexthdr 1
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 0 => reg 1 ]
[ cmp eq reg 1 0x00000001 ]
# rt nexthdr != 1
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 0 => reg 1 ]
[ cmp neq reg 1 0x00000001 ]
# rt nexthdr {udplite, ipcomp, udp, ah, sctp, esp, dccp, tcp, ipv6-icmp}
__set%d test-inet 3
__set%d test-inet 0
element 00000088 : 0 [end] element 0000006c : 0 [end] element 00000011 : 0 [end] element 00000033 : 0 [end] element 00000084 : 0 [end] element 00000032 : 0 [end] element 00000021 : 0 [end] element 00000006 : 0 [end] element 0000003a : 0 [end]
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 0 => reg 1 ]
[ lookup reg 1 set __set%d ]
# rt nexthdr != {udplite, ipcomp, udp, ah, sctp, esp, dccp, tcp, ipv6-icmp}
__set%d test-inet 3
__set%d test-inet 0
element 00000088 : 0 [end] element 0000006c : 0 [end] element 00000011 : 0 [end] element 00000033 : 0 [end] element 00000084 : 0 [end] element 00000032 : 0 [end] element 00000021 : 0 [end] element 00000006 : 0 [end] element 0000003a : 0 [end]
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 0 => reg 1 ]
[ lookup reg 1 set __set%d 0x1 ]
# rt nexthdr icmp
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 0 => reg 1 ]
[ cmp eq reg 1 0x00000001 ]
# rt nexthdr != icmp
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 0 => reg 1 ]
[ cmp neq reg 1 0x00000001 ]
# rt nexthdr 22
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 0 => reg 1 ]
[ cmp eq reg 1 0x00000016 ]
# rt nexthdr != 233
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 0 => reg 1 ]
[ cmp neq reg 1 0x000000e9 ]
# rt nexthdr 33-45
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 0 => reg 1 ]
[ cmp gte reg 1 0x00000021 ]
[ cmp lte reg 1 0x0000002d ]
# rt nexthdr != 33-45
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 0 => reg 1 ]
[ range neq reg 1 0x00000021 0x0000002d ]
# rt nexthdr { 33, 55, 67, 88}
__set%d test-inet 3
__set%d test-inet 0
element 00000021 : 0 [end] element 00000037 : 0 [end] element 00000043 : 0 [end] element 00000058 : 0 [end]
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 0 => reg 1 ]
[ lookup reg 1 set __set%d ]
# rt nexthdr != { 33, 55, 67, 88}
__set%d test-inet 3
__set%d test-inet 0
element 00000021 : 0 [end] element 00000037 : 0 [end] element 00000043 : 0 [end] element 00000058 : 0 [end]
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 0 => reg 1 ]
[ lookup reg 1 set __set%d 0x1 ]
# rt hdrlength 22
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 1 => reg 1 ]
[ cmp eq reg 1 0x00000016 ]
# rt hdrlength != 233
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 1 => reg 1 ]
[ cmp neq reg 1 0x000000e9 ]
# rt hdrlength 33-45
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 1 => reg 1 ]
[ cmp gte reg 1 0x00000021 ]
[ cmp lte reg 1 0x0000002d ]
# rt hdrlength != 33-45
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 1 => reg 1 ]
[ range neq reg 1 0x00000021 0x0000002d ]
# rt hdrlength { 33, 55, 67, 88}
__set%d test-inet 3
__set%d test-inet 0
element 00000021 : 0 [end] element 00000037 : 0 [end] element 00000043 : 0 [end] element 00000058 : 0 [end]
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 1 => reg 1 ]
[ lookup reg 1 set __set%d ]
# rt hdrlength != { 33, 55, 67, 88}
__set%d test-inet 3
__set%d test-inet 0
element 00000021 : 0 [end] element 00000037 : 0 [end] element 00000043 : 0 [end] element 00000058 : 0 [end]
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 1 => reg 1 ]
[ lookup reg 1 set __set%d 0x1 ]
# rt type 22
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 2 => reg 1 ]
[ cmp eq reg 1 0x00000016 ]
# rt type != 233
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 2 => reg 1 ]
[ cmp neq reg 1 0x000000e9 ]
# rt type 33-45
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 2 => reg 1 ]
[ cmp gte reg 1 0x00000021 ]
[ cmp lte reg 1 0x0000002d ]
# rt type != 33-45
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 2 => reg 1 ]
[ range neq reg 1 0x00000021 0x0000002d ]
# rt type { 33, 55, 67, 88}
__set%d test-inet 3
__set%d test-inet 0
element 00000021 : 0 [end] element 00000037 : 0 [end] element 00000043 : 0 [end] element 00000058 : 0 [end]
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 2 => reg 1 ]
[ lookup reg 1 set __set%d ]
# rt type != { 33, 55, 67, 88}
__set%d test-inet 3
__set%d test-inet 0
element 00000021 : 0 [end] element 00000037 : 0 [end] element 00000043 : 0 [end] element 00000058 : 0 [end]
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 2 => reg 1 ]
[ lookup reg 1 set __set%d 0x1 ]
# rt seg-left 22
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 3 => reg 1 ]
[ cmp eq reg 1 0x00000016 ]
# rt seg-left != 233
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 3 => reg 1 ]
[ cmp neq reg 1 0x000000e9 ]
# rt seg-left 33-45
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 3 => reg 1 ]
[ cmp gte reg 1 0x00000021 ]
[ cmp lte reg 1 0x0000002d ]
# rt seg-left != 33-45
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 3 => reg 1 ]
[ range neq reg 1 0x00000021 0x0000002d ]
# rt seg-left { 33, 55, 67, 88}
__set%d test-inet 3
__set%d test-inet 0
element 00000021 : 0 [end] element 00000037 : 0 [end] element 00000043 : 0 [end] element 00000058 : 0 [end]
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 3 => reg 1 ]
[ lookup reg 1 set __set%d ]
# rt seg-left != { 33, 55, 67, 88}
__set%d test-inet 3
__set%d test-inet 0
element 00000021 : 0 [end] element 00000037 : 0 [end] element 00000043 : 0 [end] element 00000058 : 0 [end]
inet test-inet input
[ meta load nfproto => reg 1 ]
[ cmp eq reg 1 0x0000000a ]
[ exthdr load 1b @ 43 + 3 => reg 1 ]
[ lookup reg 1 set __set%d 0x1 ]
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